| 1 |
Title
A Novel Low- Dynamic Comparator Leveraging Cascaded Structure for Noise Minimization Power
Authors admin
| 1-3 |
| 2 |
Title
Power-Aware Full Adder Design Using Hybrid CMOS Logic with 16-Transistor Architecture
Authors admin
| 4-9 |
| 3 |
Title
Design and Implementation of a Fin FET-Based Hybrid Full Adder Using GDI in 18nm CMOS
Authors admin
| 17-19 |